Advanced heterogeneous memory subsystems for energy-constrained computing
von Deepak Molly MathewAbstract
The performance and energy efficiency of today’s computing systems are limited by the
underlying main memory architectures. This is due to the widening gap between the CPU
performance and the main memory (DRAM) performance (memory wall), as well as the
proliferation of several memory-centric applications that demand higher bandwidth, lower
access latency, larger capacity, and improved energy efficiency from the main memory.
Moreover, DRAMs can not keep pace with the required main memory capacities because
of the restrictions in improving the cell density due to the slowdown in scaling and the
high leakage power consumption. Emerging Non-Volatile Memory (NVM) technologies,
specifically Metal Oxide Resistive Random Access Memory (RRAM), is a promising alternative
to DRAM as it offers higher capacity, scalability, and better energy efficiency.
However, RRAMs suffer from large access latencies and limited write endurance, making
their integration into the main memory subsystem challenging. RRAM technology is still
in research or the early stages of production, and thus, there are no accurate architectural
models available for system-level design space explorations.
This thesis conducted scientific investigations to optimize DRAM as well as to incorporate
RRAM into the main memory. The significant outcomes of DRAM research are the
advanced refresh techniques and retention error models to optimize DRAM refresh, and an
advanced measurement platform to validate these techniques and models via conducting
measurements on off-the-shelf commodity DRAMs. The integration of RRAM requires
restructuring of the entire main memory subsystem. The primary research contributions
in this direction include models and an architectural exploration framework for RRAMs,
the architecture of a new 3D-hybrid main memory consisting of DRAM and RRAM, joint
design space explorations of the hybrid memory and its controller using hardware and software
techniques, and investigations on specific applications for this new memory architecture.
The performance and energy efficiency of today’s computing systems are limited by the
underlying main memory architectures. This is due to the widening gap between the CPU
performance and the main memory (DRAM) performance (memory wall), as well as the
proliferation of several memory-centric applications that demand higher bandwidth, lower
access latency, larger capacity, and improved energy efficiency from the main memory.
Moreover, DRAMs can not keep pace with the required main memory capacities because
of the restrictions in improving the cell density due to the slowdown in scaling and the
high leakage power consumption. Emerging Non-Volatile Memory (NVM) technologies,
specifically Metal Oxide Resistive Random Access Memory (RRAM), is a promising alternative
to DRAM as it offers higher capacity, scalability, and better energy efficiency.
However, RRAMs suffer from large access latencies and limited write endurance, making
their integration into the main memory subsystem challenging. RRAM technology is still
in research or the early stages of production, and thus, there are no accurate architectural
models available for system-level design space explorations.
This thesis conducted scientific investigations to optimize DRAM as well as to incorporate
RRAM into the main memory. The significant outcomes of DRAM research are the
advanced refresh techniques and retention error models to optimize DRAM refresh, and an
advanced measurement platform to validate these techniques and models via conducting
measurements on off-the-shelf commodity DRAMs. The integration of RRAM requires
restructuring of the entire main memory subsystem. The primary research contributions
in this direction include models and an architectural exploration framework for RRAMs,
the architecture of a new 3D-hybrid main memory consisting of DRAM and RRAM, joint
design space explorations of the hybrid memory and its controller using hardware and software
techniques, and investigations on specific applications for this new memory architecture.